This present disclosure relates generally to formal verification of circuit designs, and more particularly to formal verification methods of verifying deadlock conditions in multi-system circuits.
Highly-integrated complex system-on-chip (SoC) devices power a wide range of systems, ranging from mobile computing devices to automotive control systems. One factor aiding the advancement and proliferation of these complex devices includes the use of readily available reusable semiconductor intellectual property (IP). Reusable semiconductor IP provides designers with a variety of silicon proven subsystem blocks, including processors, memory controllers, physical interfaces (PHYs), and input/output (I/O) circuits. But the integration of reusable semiconductor IP also adds to the growing challenges facing design verification engineers.
Multisystem SoCs present complex system issues that can be difficult and time consuming to identify and solve, even for experienced design verification engineers. These issues include verifying that multiple subsystems operate as a system and stressing subsystem interfaces to fully characterize and verify transaction flow between subsystem modules. While verification tools have improved, current verification methods still require significant expertise and experience to quickly identify and debug complex interface and interconnect problems. And, in many cases, verification tools lack the capability to interact with verification engineers in a manner to leverage their expertise to address this complexity.
To improve system-oriented SoC verification, what are needed are techniques that leverage information from individual pieces in verifying global behavior of the system, and also leverage collaborative interaction with the verification engineer to aid in the identification and resolution of complex interface and interconnect problems associated with multi-system SoCs.